The memory cells and their structural features are submitted to a steady process of diminution in order to reduce the area of the cell array and to achieve an ever-growing storage density. This development is to some degree adverse to the requirements of the complementary transistors forming the addressing logic circuits arranged in the periphery of the memory cell array and usually produced in standard CMOS technology, which renders devices of larger dimensions. It is a heretofore unresolved problem how memory cells comprising transistor structures on a scale of typically 70 nm, especially charge-trapping memory cells, can be integrated with CMOS devices of much larger dimensions on the same semiconductor substrate by a process that does not deviate significantly from standard manufacturing processes.
Memory devices with charge-trapping layers, especially SONOS memory cells comprising oxide-nitride-oxide layer sequences as storage medium, are usually programmed by channel hot electron injection. U.S. Pat. No. 5,768,192 and U.S. Pat. No. 6,011,725, which are incorporated herein by reference, disclose charge-trapping memory cells of a special type of so-called NROM cells, which can be used to store bits of information both at the source and at the drain below the respective gate edges. The programmed cell is read in reverse mode to achieve a sufficient two-bit separation. Erasure is performed by hot hole injection.
U.S. Patent Application Publication 2003/0185055 A1 and a corresponding paper of C. C. Yeh et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory”, 2002 IEEE, which are incorporated herein by reference, disclose a non-volatile semiconductor memory cell with electron-trapping erase state, which is operated as flash memory and is able to store two bits. The erasure takes place by Fowler-Nordheim tunneling of electrons from either channel or gate electrode into the storage layer of a conventional charge-trapping layer sequence, for example an ONO layer sequence. In programming this memory, electric holes are injected into the non-conducting charge-trapping layer. Hot hole injection can be induced at source and drain, which means, at both ends of the channel.
The memory layer can be substituted with another dielectric material, provided the energy band gap is smaller than the energy band gap of the confinement layers. The difference in the energy band gaps should be as great as possible to secure a good charge carrier confinement and thus good data retention. Especially when silicon dioxide is used as confinement layers, the memory layer can be tantalum oxide, hafnium silicate, cadmium silicate, titanium oxide, zirconium oxide, aluminum oxide, or intrinsically conducting (non-doped) silicon. The memory layer can also comprise electrically insulating or conducting nano dots, which are small particles having diameters of a few nanometers and are located in a layer of dielectric material.